Emulation is a critical capability that enables software flexibility and platform resourcefulness. As the leading architecture today, “Arm” powers the chips in billions of devices. To leverage the vast ecosystem of software built for other architectures, “Arm” chips incorporate the emulation of “x86” and “Arm32” instruction sets. Emulation allows software compiled for other architectures to run on Arm-based systems unmodified. Through a combination of hardware and software, “Arm” chips can interpret instructions from “x86” and “Arm32” binaries and execute them as if they were native Arm code.

This blog uncovers the working of “x86” and “Arm32” emulation on Arm and explains the following content:

• How Arm Translates X86 Instructions?
• The Challenges of Emulating Arm32.
• Arm and Seamless Emulation of x86 and Arm32.

How Arm Translates X86 Instructions?

“Arm” chips can emulate “x86” and “Arm32” instructions flawlessly through a process known as “Dynamic Translation”. Arm’s emulation technology translates “x86” and “Arm32” instructions into native “Arm” instructions that provide the same functionality.

To emulate “x86” instructions, the “Arm” chip decodes each “x86” instruction and breaks it down into a series of simpler Arm instructions replicating the original function. The decoded “x86” instructions are stored in a “Translation Cache”, so if the same “x86” instruction is used again, the “Arm” chip can quickly look it up and execute the translated “Arm” instructions.

The translation process requires processing power and memory resources, which reduces the performance of emulated x86 and Arm32 code compared to native Arm code. However, Arm has significantly improved performance over time by continuously optimizing its emulation technology.

Emulated x86 and Arm32 applications can now run at near-native speeds on many Arm-based platforms.

Emulation is a complex process, but Arm’s technology has matured to the point where x86 and Arm32 emulation on Arm chips are seamless, enabling a wide range of use cases where binary translation and compatibility are required.

What is “Translation Cache”?

The “Translation Cache” is a key component that enables fast and efficient emulation. As more “x86” instructions are translated, the “Translation Cache” fills up, speeding up the emulation of those instructions. It is optimized to only store actively used translations. If a translation is not used for some time, it is removed from the cache.

The Challenges of Emulating “Arm32”

To emulate the “Arm32” instruction set architecture on Arm-based chips requires overcoming several significant challenges.

1. “Arm32” and “Arm” have different instruction encodings, so the emulator must translate “Arm32” instructions into the native “Arm” instructions. This translation requires mapping the “32-bit Arm32” registers to the “64-bit Arm” registers while preserving their definition.
2. The emulator must handle the differences in operating modes between the architectures. “Arm32” has seven operating modes, while “Arm” has two. The emulator must track the current operating mode and modify the behavior of instructions accordingly.
3. The conditional execution poses difficulties, as the condition codes and conditional execution of instructions differ between “Arm32” and “Arm”. The emulator must evaluate the “Arm32” condition codes and conditionally execute “Arm” instructions to achieve the same effect.

Arm and Seamless Emulation of “x86” and “Arm32”

The “Arm” utilizes the following methods/techniques to emulate the “x86” and “Arm32 seamlessly”:

Seamless Binary Translation

Arm’s approach to emulation, enables the seamless execution of “x86” and “Arm32” binaries on Arm-based devices. Arm’s binary translation technology converts the source instruction set architecture (ISA) ‘s machine code into the target ISA’s machine code at runtime. This allows apps and software compiled for “x86” and “Arm32” to run unmodified on Arm-based systems.

Efficient Dynamic Recompilation

The emulation software dynamically recompiles blocks of “x86” and “Arm32” instructions into the native “Arm” code. It decodes each source instruction and generates an “Arm” instruction sequence that performs the same operation. The recompiled “Arm” code is then cached to avoid re-translating the same instructions multiple times. This efficient translation and caching process ensures fast and seamless source ISA emulation.

Hardware Acceleration Support

Arm’s approach leverages dedicated hardware components like the “Memory Management Unit (MMU)” and “Branch Target Buffer (BTB)” to accelerate the emulation of “x86” and “Arm32” binaries. The “MMU” is used to implement memory segmentation and paging, while the “BTB” predicts the outcomes of conditional branches. This hardware-based acceleration works with the dynamic binary translation to enable full-system emulation of the source architectures at near-native speeds.

That is all about working of “x86” and “Arm32” emulation on native Arm.

Conclusion

“Arm” chips can run “x86” and “Arm32” software with impressive performance and efficiency through dynamic translation, caching, and optimization. With near-native speed emulation, “Arm” chips can run a huge library of legacy “Windows”, “Linux”, and “macOS” applications. This guide explained the working of “x86” and “Arm32” emulation on “Arm”.